# KiCad Desk

> Paste the KiCad files you are about to send to a board house - a `.kicad_sch`, a `.kicad_pcb`, or
> both - and work the project to order-ready in one sitting. A real S-expression parser runs free in
> the browser; four AI lanes then read, review and check the same files.

Live at https://kicad-desk.skillsafe.ai/ . Built on the SkillSafe apps platform. The browser side needs
no account and no network call. The four AI lanes are metered and need a signed-in SkillSafe account.

## What runs for free, in the browser

No account, no upload, no model. All of it is a real parse of the files, not a keyword search: a
`.kicad_sch` and a `.kicad_pcb` are each one S-expression, and the reader is a character-state pass, so
a parenthesis inside a quoted string is not a parenthesis and a parse failure reports a line and a
column.

Schematic side:

- Symbol inventory: every instance with its `lib_id`, designator, value, footprint, datasheet, unit,
  DNP and BOM-exclusion flags, and every extra property including sourcing fields (LCSC, MPN,
  manufacturer part number, distributor codes).
- Annotation audit: duplicate designators, unannotated parts (`C?`), designators whose prefix disagrees
  with the symbol they are on (a `Device:R` called `C9`), symbols with no Reference at all, and
  identical symbols stacked at exactly one coordinate.
- Library audit: any `lib_id` used by a placed symbol with no matching definition in `lib_symbols` -
  which KiCad never writes, so it means the file was hand-edited, merged or truncated.
- Footprint audit: parts in the BOM with an empty Footprint property, footprints with no library
  prefix, and value-versus-footprint package conflicts (a value that says 0603 on an 0805 footprint).
- Component values parsed the six idiomatic ways engineers write them - `10k`, `4k7`, `4.7k`, `100nF`,
  `2u2`, `0R` - so `4k7` and `4.7k` roll up as one BOM line. Unit-less capacitor values are flagged
  because a bare `100` is 100pF to one tool and 100nF to another. Resistor values more than 3% from the
  nearest E24 value are flagged as probable typos.
- Wire-level netlist: nets derived from wire, bus, junction, label, global label, hierarchical label
  and power-symbol geometry, with labels that touch no wire, power symbols sitting on no wire, and one
  wire net carrying two different names all called out.
- BOM roll-up grouped by normalised value, footprint, library and part number, with quantities and
  designator lists.

Board side:

- Outline: whether Edge.Cuts is closed, proved endpoint by endpoint - every line and arc end must be
  shared with exactly one other end - plus the bounding box, its area, and the count of unmatched ends.
- Stackup: copper layer count and names, board thickness from `(general (thickness ...))`.
- Copper: track count and narrowest width per layer, total copper length, via count with the smallest
  diameter, drill and annular ring, zones with their nets and minimum thickness, and any net declared
  in the net table with no copper on the board at all.
- Holes: the closest pair of drilled holes, measured within each footprint (where distances are
  placement-invariant, so exact) and between vias. Cross-footprint pairs are not measured and the
  read-out says so.
- Copper to board edge, measured from tracks and vias to the outline bounding box - an upper bound on a
  non-rectangular board, labelled as one.
- Silkscreen: the thinnest stroke and the smallest text height anywhere on a silk layer.
- Fab capability check against a selectable profile (JLCPCB 2-layer, JLCPCB 4-layer, PCBWay 2-layer, or
  none), with the required and the measured number side by side for every rule.

Both files together:

- Cross-check: parts in the schematic with no footprint on the board, footprints on the board with no
  schematic symbol (separating the ones that are expected to be board-only, like mounting holes),
  footprint disagreements, value disagreements and DNP disagreements.

Exports, all free:

- An assembly BOM CSV in the column order an assembly house reads: Comment, Designator, Footprint,
  Quantity, Part Number, DNP, Symbol Library.
- A position file CSV: Designator, Mid X, Mid Y, Layer, Rotation - taken straight from each footprint's
  own placement values, with no coordinate transform, so nothing in it can be quietly wrong about a
  rotated part. Footprints the board marks as excluded from position files are left out.
- A parsed-project JSON with the wire-level nets, the parts, the board measurements and the fab check.
- The whole read-out as Markdown.

## The four AI lanes

One model, one system prompt, an explicit `task` field. Every lane reads the same paste.

| `task` | What it does |
| --- | --- |
| `decode` | Reads the files construct by construct and says what the design appears to be |
| `review` | Reviews the schematic across nine areas and returns a corrected S-expression fragment |
| `layout` | Reviews the board across nine areas against the fab profile, with rule advice |
| `fab` | Says whether the project can be ordered: gates, BOM actions, checklist, cost drivers |

Each result offers the next lane as a button, and the board and order lanes carry the schematic
review's findings forward when there is one.

## How the AI pass is kept honest

- The browser measures first and its facts go into the run. The model is told that `prescan` is
  authoritative on counts and measurements, and that a clipped file was clipped.
- Every flag the browser raised at high or medium severity must come back with a reconciliation entry.
  One that does not is displayed as unaccounted for rather than quietly dropped.
- Every designator, net and layer the model cites is checked against the set the pasted files actually
  contain. One that does not exist is shown, marked, not hidden.
- A corrected S-expression fragment is re-parsed in the browser with the same reader before it is
  displayed, and an unbalanced fragment says so.
- The prompt forbids asserting that a component pin is unconnected, because the browser deliberately
  does not resolve pin positions; forbids saying a board cannot be manufactured (a failed check is two
  numbers disagreeing); forbids presenting the review as KiCad's own ERC or DRC; and forbids stating a
  price, a lead time or a stock level as fact.

## Input and output contract

Input object: `task`, `sch_text`, `pcb_text`, `fab_profile`, `design_note`, `prescan`, and optionally
`clip_note`, `prior_review`, `retry_note`. Output is a single JSON object with `task`, `task_inferred`,
`title`, `verdict` (`order-ready`, `fix-first`, `not-ready`, `unreadable`), `summary`, `assumptions`,
`open_questions`, `findings`, `reconciliation`, `next_lane` and a per-lane `body`. The full contract,
with one worked example per lane in cURL, Python, JavaScript, Go, Java, Ruby, PHP and C#, is at
https://kicad-desk.skillsafe.ai/api.html .

## Limits, said out loud

- Connectivity is wire-level. Component pin positions live in `lib_symbols` in the symbol's own frame
  and would have to be pushed through each instance's rotation and mirror; getting that transform
  subtly wrong yields a netlist that is confidently wrong at every rotated symbol, so it is not
  attempted. A connection made only through pins is therefore not listed, and no pin is ever reported
  as unconnected.
- A hierarchical design is analysed one sheet at a time. Sub-sheets referenced by a `(sheet ...)` block
  are named and flagged, not fetched - only what you pasted is analysed.
- The fab profile numbers are this app's record of published vendor capabilities for one process, shown
  next to every measurement. They are not a quote and they change with order options.
- This is not KiCad's DRC or ERC and not a substitute for either.

## Sources

A derived work inspired by four published agent skills, credited in the app footer:

- `@o2scale/kicad-file-format` - the KiCad S-expression file format for `.kicad_sch` and `.kicad_pcb`.
  https://github.com/o2scale/electronics-agent-kit
- `@l3wi/eda-schematics` - schematic capture and wiring. https://github.com/l3wi/claude-eda
- `@l3wi/eda-pcb` - PCB layout, routing and design rules for manufacturability.
  https://github.com/l3wi/claude-eda
- `@aklofas/jlcpcb` - fabrication and assembly ordering, BOM and position files, design rules.
  https://github.com/aklofas/kicad-happy

The in-browser parser, the audits, the board measurements, the fab profiles and the exports are an
independent implementation written for this app. Not affiliated with those authors, with the KiCad
project, or with any board house.

## Pages

- https://kicad-desk.skillsafe.ai/ - the app
- https://kicad-desk.skillsafe.ai/api.html - the API tutorial, eight languages
- https://kicad-desk.skillsafe.ai/tokens.html - token management (noindex)